The present invention relates generally to the fabrication of semiconductor devices, and more particularly, to the fabrication of solder bump structures in the packaging of semiconductor devices.
Under bump metallization (UBM) structures are often utilized during semiconductor manufacturing processes. Semiconductor manufacturing processes generally begin with processes associated with fabricating a semiconductor wafer such as layering, patterning, doping, and heat treatments. Once fabricated, semiconductor wafers undergo additional processes associated with testing, packaging, and assembling semiconductor IC chips obtained from the wafers. Semiconductor manufacturing processes are continually being refined, modified, and improved in light of breakthroughs in semiconductor technology. One such technology that has continued to gain increased acceptance is “flip chip” technology, which refers to microelectronic assemblies in which direct electrical connections between face down, or flipped, chip components and outside components (e.g. substrates) are achieved through conductive bump or bonding pads formed on the chip.
Bonding pads in flip chips are typically manufactured to include a final metal layer, such as aluminum, to facilitate electrical communication from the IC chip. Flip chips are also manufactured to include solder bumps, which are deposited onto the bonding pads of such chips to physically and electrically connect the bonding pads with electrode terminals provided on packaging such as ceramic substrates, printed circuit boards, or carriers. Solder bumps are typically formed of a metal alloy such as a lead-tin alloy, and are often applied to semiconductor wafers prior to separation into individual semiconductor chips.
Solder bumps, however, are generally not applied directly to the bonding pads of the semiconductor wafer. It has been found that the direct application of solder bump material to the semiconductor wafer yields poor electrical conduction, due largely to the rapid oxidation of the final metal layer (e.g. aluminum) upon exposure to air. Moreover, aluminum has been found to be neither particularly wettable nor bondable with most solders. Accordingly, UBM structures and associated techniques have been developed to provide a low resistance electrical connection between the solder bump and the underlying bonding pad, while withstanding the various stresses associated with semiconductor applications.
UBM structures generally include one or more metallic layers, such as layers of titanium and of copper, deposited over the bonding pads of IC chips. In practice, solder is typically deposited over a UBM structure, and then heated via a reflow process to form a generally spherical solder bump. However, it has been found that prior art solder bump structures tend to suffer from poor reliability and performance due to the problem of undercutting in one or more of the UBM layers.
FIGS. 1A-1D illustrate this problem. FIG. 1A depicts a cross-sectional view of a conventional solder bump structure during a fabrication process, the structure containing the following:
2 is a semiconductor substrate over which the solder bump is to be formed.
4 is the bonding pad, which is to be brought into contact with the solder bump to be formed.
6 is a patterned passivation layer.
8A is a first UBM layer (e.g. titanium).
8B is a second UBM layer (e.g. copper).
10 is a mask layer (e.g. photoresist).
12 is an opening in the mask layer.
Typically, additional layers of UBM may be deposited in opening 12 of the mask layer 10. In FIG. 1B, additional layers of copper (8B) and nickel (8C) are deposited in opening 12 filling a portion of the mask layer 10. Following the removal of the mask layer 10 as shown in FIG. 1C, the UBM layers undergo an etching step, such as wet etching. First, nickel layer 8C is etched, then the copper layers 8B, and finally the adhesive titanium layer 8A. In wet etching, an isotropic etch profile is produced, in which the etching is at the same rate in all directions, leading to undercutting of the etched material. This action results in an undesirable loss of linewidth. In etching the copper layers 8B, an undercut 14 results as shown in FIG. 1D. Due to its thickness, the copper needs to be exposed to the etchant for a longer period resulting in an undercut. In etching the titanium layer 8A, an undercut 16 results. Copper undercut 14 may be as large as 6 μm per side and titanium undercut 16 may be as large as 4 μm per side, resulting in a total undercut of 10 μm per side of the solder bump structure. Although the undercut is an inherent result of the etching process, the undercut is detrimental to the long term reliability of the interconnection. The undercut compromises the integrity of the solder bump structure by weakening the bond between the solder bump and the bonding pad of the chip, thereby leading to premature failure of the chip.
For these reasons and other reasons that will become apparent upon reading the following detailed description, there is a need for a solder bump structure having improved reliability and performance that avoids the undercut problems associated with conventional solder bump structures.